TSMC’s FinFlex Technology Enables Better Design Flexibilty
According to TSMC, FinFlex gives it better design flexibility and makes it easier for chip designers to fine tune performance and power consumption, balanced with cost, all while maximizing transistor density. This is especially important as the market as a whole embraces hybrid CPU designs.
“The TSMC FinFlex innovation offers choices of different standard cells with a 3-2 fin configuration for ultra performance, a 2-1 fin configuration for best power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two for Efficient Performance,” TSMC explains.
Shown in the image above is an example of an N3 layout where the chip designer can choose the ideal Fin configuration for each functional block on a chip. A 3-2 Fin enables the fastest clock frequencies and best performance; a 2-2 Fin arrangement offers a balance between performance, power efficiency, and density; and a 2-1 Fin enables the lowest power consumption with the lowest leakage and highest density of the bunch.
Note that FinFlex does not replace customized nodes and specialized libraries, but it’s another way that chip designers can tune their designs based on their power, performance, and cost goals.
TSMC Looks Ahead To 2 Nanometers (2N) In 2025
The other technological introduction with N2 is a backside power rail. This goes hand-in-hand with GAAFETs to improve the performance-per-watt proposition.
TSMC claims its N2 technology will deliver a 10-15 percent speed improvement at the same power versus N3E, or a 25-30 percent power reduction at the same speed. This, according to TSMC, will usher in a new era of efficient performance.
“N2 will feature nanosheet transistor architecture to deliver a full-node improvement in performance and power efficiency to enable next-generation product innovations from TSMC customers. The N2 technology platform includes a high-performance variant in addition to the mobile compute baseline version, as well as comprehensive chiplet integration solutions,” TSMC says.
Interestingly, the improvement in transistor density will in the neighborhood of 10 percent versus N3E. That’s not earth shattering, and N3S could close the gap, albeit on a different process technology. That could set the state for some interesting chip design decisions down the line.
